The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, it relates to a method of manufacturing a bipolar semiconductor memory device.
2. Description of the Background Art
A bipolar semiconductor memory device generally comprises memory element group and peripheral circuits such as an I/O circuit. The memory element group comprises memory cells which are arranged in the form of a matrix in a memory element area. Each memory cell is provided with a flip-flop circuit comprising a bipolar transistors. The peripheral circuits are arranged in a peripheral circuit area.
In the aforementioned memory cells, soft errors are easily caused by alpha rays incident upon the semiconductor memory device. Namely, when a prescribed amount of electron-hole pairs are generated upon incidence of the alpha rays in the semiconductor memory device, data stored in the memory cells are inverted, to thereby cause soft errors. The amount of such electron-hole pairs required for inverting the data stored in the memory cells is called a critical charge amount. Thus, it is effective to increase the critical charge amount in order to prevent the soft errors.
In recent years, however, such a bipolar semiconductor memory device has been increasingly refined in order to cope with requirement for implementation of the bipolar semiconductor memory device with a higher degree of integration and a higher operating speed. Thus, the amount of charges storable in the memory cells has been reduced, and the critical charge amount is accordingly decreased. In other words, the memory cells have increasingly suffered from soft errors caused by alpha rays with increase in the degree of integration and the operating speed of the bipolar semiconductor memory device.
In order to solve such a problem, collector layers of transistors forming memory cells have been generally reduced in thickness to increase base-to-collector parasitic capacitance, to thereby increase the critical charge amount of the memory cells. In more concrete terms, the bipolar semiconductor memory device has been generally manufactured through the following procedure:
FIGS. 1A to 1E are sectional views for illustrating a method of manufacturing a conventional bipolar semiconductor memory device.
(1) First, N.sup.+ -type subcollector regions 2a to 2d are formed at regular intervals in an upper layer part of a P.sup.- -type semiconductor substrate 1 by ion implantation, selective diffusion or the like, as shown in FIG. 1A. Then, an N.sup.- -type collector layer 3 is epitaxially grown on the P.sup.- -type semiconductor substrate 1 and the N.sup.+ -type subcollector regions 2a to 2d. Referring to FIG. 1A, symbols M and S indicate a memory element area and a peripheral cricuit area respectively.
(2) Then, an SiO.sub.2 layer 4 is formed in an upper layer part of the N.sup.- -type collector layer 3 corresponding to the memory element area M by well-known LOCOS (local oxidation of silicon) process, as shown in FIG. 1B.
(3) Thereafter the SiO.sub.2 layer 4 is entirely removed, as shown in FIG. 1C. Thus, a cavity 30 is formed into an upper side part of the N.sup.- -type collector layer 3 corresponding to the memory element area M, to thereby reduce thickness of the N.sup.- -type collector layer 3.
(4) Then, SiO.sub.2 layers 5a, 5b, 5c, 5d and 5e are respectively formed by the LOCOS process, and element forming regions M1, M2, S1 and S2 are defined between adjacent pairs of the SiO.sub.2 layers 5a, 5b, 5c, 5d and 5e, as shown in FIG. 1D. Namely, the element forming region M1 formed by the N.sup.+ -type subcollector region 2a and an N.sup.- -type collector region 3a is isolated from its peripheral region by the SiO.sub.2 layers 5a and 5b. In a similar manner, the element forming regions M2, S1 and S2 are also isolated from peripheral regions thereof, respectively.
(5) Finally, bipolar transistors for forming memory cells are respectively provided in the element forming regions M1 and M2, while elements, such as transistors and resistors, for forming the peripheral circuit are respectively provided in the element forming regions S1 and S2 by well-known technique, as shown in FIG. 1E. Referring to FIG. 1E, for example, NPN bipolar transistors Q.sub.a and Q.sub.b for forming memory cells are provided in the element forming regions M1 and M2, while NPN bipolar transistors Q.sub.c and Q.sub.d for forming peripheral circuits are provided in the element forming regions S1 and S2, respectivly. To say more precisely, and N.sup.+ -type subcollector region 6a is formed in a part of the N.sup.- -type collector region 3a to be coupled with the N.sup.+ -type subcollector region 2a. Further, a P.sup.+ -type base region 7a is formed in an upper layer part of the N.sup.- -type collector region 3a, while an N.sup.+ -type emitter region 8a is formed in an upper layer part of the P.sup.+ -type base region 7a. Namely, the NPN bipolar transistors Q.sub.a comprises the N.sup.- -type collector region 3a, the P.sup.+ -type base region 7a and the N.sup.+ -type emitter region 8a. Similarly to the NPN bipolar transistors Q.sub.a, the NPN bipolar transistors Q.sub.b, Q.sub.c and Q.sub.d are formed in the element forming regions M2, S1 and S2, respectively. Components of the NPN bipolar transistors Q.sub.b, Q.sub.c and Q.sub.d are indicated by corresponding numerals, and redundant description thereof is omitted.
As hereinabove described, the collector regions 3a, 3b (N.sup.- -type collector layer 3) of the transistors Q.sub.a and Q.sub.b for forming the memory cells are respectively reduced in thickness by the steps (2) (FIG. 1B) and (3) (FIG. 1C), to thereby increase base-to-collector parasitic capacitance. Consequently, the critical charge amount is also increased, and occurrence of soft errors is accordingly reduced.
In the aforementioned manufacturing method, however, the element forming regions M1, M2, S1 and S2 are defined between adjacent pairs of the SiO.sub.2 layers 5a, 5b, 5c, 5d and 5e formed by the LOCOS process in the step (4), whereby bird's beaks are caused on respective both end portions of the SiO.sub.2 layers 5a, 5b, 5c, 5d and 5e formed by the LOCOS process to narrow the N.sup.- -type collector regions 3a, 3b, 3c and 3d, as shown in FIG. 1D. Consequently, the degree of integration of the semiconductor memory device cannot be improved.
Therefore, a trench isolation process has been proposed as a new element isolation method for taking the place of the LOCOS process. In more concrete terms, a bipolar semiconductor memory device is manufactured in the following procedure:
FIGS. 2A to 2E are sectional views for illustrating a method of manufacturing the bipolar semiconductor memory device according to such a proposal.
(1) First, an N.sup.+ -type subcollector layer 2 is formed in an upper layer part of a P.sup.- -type semiconductor substrate 1 by ion implantation, selective diffusion or the like, and then an N.sup.- -type collector layer 3 is epitaxially grown on the N.sup.+ -type subcollector layer 2, as shown in FIG. 2A.
(2) Then, an SiO.sub.2 layer 4 is formed by the LOCOS process in an upper layer part of the N.sup.- -layer collector layer 3 corresponding to a memory element area M, as shown in FIG. 2B.
(3) Thereafter the SiO.sub.2 layer 4 is entirely removed as shown in FIG. 2C, to thereby form a cavity 30 in the N.sup.- -type collector layer 3 corresponding to the memory element area M. Thus, thickness of the N.sup.- -type collector layer 3 corresponding to the memory element area M is reduced.
(4) Then, SiO.sub.2 layers 9 are respectively formed in prescribed regions of the upper layer part of the N.sup.- -type collector layer 3 corresponding to a peripheral circuit area S by the LOCOS process, as shown in FIG. 2D. The regions provided with the SiO.sub.2 layers 9 are adapted to serve as wiring regions of the semiconductor memory device in a later step, and wires are so provided on the SiO.sub.2 layers 9 as to increase the distance d between the semiconductor substrate 1 and the wires. Consequently, parasitic capacitance across the semiconductor substrate 1 and the wires is reduced, and it is accordingly possible to get the semiconductor memory device of high-speed operation. In the aforementioned conventional method shown in FIGS. 1A to 1E, the SiO.sub.2 layers 5c and 5e formed in the step (4) (FIG. 1D) have the function similarly to the SiO.sub.2 layers 9.
(5) Thereafter trench isolation members 10a to 10f are formed in prescribed positions of the memory element area M and the peripheral circuit area S by a well-known trench isolation method as shown in FIG. 2E, while element forming regions M1, M2, S1 and S2 are defined between adjacent pairs of the trench isolation members 10a to 10f. Namely, the element forming region M1 comprising an N.sup.+ -type subcollector region 2a and an N.sup.- -type collector region 3a is isolated from its peripheral region by the trench isolation members 10a and 10b. Similarly, the element forming regions M2, S1 and S2 are also isolated from peripheral regions thereof, respectively.
(6) Finally, bipolar transistors for forming memory cells are respectively provided in the element forming regions M1 and M2, while elements, such as transistors, resistors or the like, for forming the peripheral circuit are respectively provided in the element forming regions S1 and S2 by well-known technique similarly to the step (5) (FIG. 1E) of the aforementioned conventional method, as shown in FIG. 2E. Referring to FIG. 2E, NPN bipolar transistors Q.sub.a and Q.sub.b for forming memory cells are provided in the element forming regions M1 and M2, while NPN bipolar transistors Q.sub.c and Q.sub.d for forming peripheral circuits are provided in the element forming regions A1 and S2, respectively, similarly to the case of FIG. 1E. The NPN bipolar transistors Q.sub.q to Q.sub.d shown in FIG. 2E are identical to those of FIG. 1E, and hence redundant description is omitted.
Thus, according to the method of manufacturing a semiconductor memory device shown in FIGS. 2A to 2E, collector regions 3a and 3b (N.sup.- -type collector layer 3) of the transistors Q.sub.a and Q.sub.b for forming the memory cells are reduced in thickness through the steps (2) (FIG. 2B) and (3) (FIG. 2C), to thereby increase base-to-collector parasitic capacitance similarly to the aforementioned conventional method. Consequently, the critical charge amount is also increased, and occurrence of soft errors is accordingly reduced. Further, the degree of integration of the semiconductor memory device can be improved since the trench isolation members 10a to 10f are formed in the step (5) (FIG. 2E) to isolate the element forming regions M1, M2, S1 and S2 from each other.
In the method of manufacturing a semiconductor memory device according to the aforementioned proposal, however, the steps of manufacturing the semiconductor memory device are complicated since the step (2) (FIG. 2B) of forming the SiO.sub.2 layer 4 and the step (4) (FIG. 2D) of forming the SiO.sub.2 layers 9 are separately performed, whereby the manufacturing efficiency of the semiconductor memory device is lowered.
In general, mask alignment must be performed in consideration of errors following thereto, and hence it is necessary to perform pattern design with allowance for such errors caused upon mask alignment. Therefore, the number of times of mask alignment is preferably reduced to the minimum in order to improve the degree of integration of the semiconductor memory device. In the method of manufacturing a semiconductor memory device according to the aforementioned proposal, however, mask alignment is required at least twice since the SiO.sub.2 layer 4 and the SiO.sub.2 layers 9 are separately formed, and hence the degree of integration of the semiconductor memory device is reduced. In order to solve such a problem, the ste (4) (FIG. 2D) of forming the SiO.sub.2 layers 9 may be omitted. However, the SiO.sub.2 layers 9 are adapted to reduce parasitic capacitance across the semiconductor substrate 1 and the wires to contribute to high-speed operation of the semiconductor memory device as hereinabove described. Thus, it is not preferable to omit the step (4) (FIG. 2D) since characteristics of the semiconductor memory device will be degraded by such omission of the step (4).